DS80C400 datasheet(14/97 Pages) DALLAS

14 / 97 page

DS80C400 Network Microcontroller

14 of 97

MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V +±10%, TA = -40°C to +85°C.)

PARAMETER

SYMBOL

MIN

MAX

UNITS

STRETCH

VALUES

CST (MD2:0)

2tCLCL - 5

CST = 0

3tCLCL - 5

£ CST £ 3

Input Instruction Float After

PSEN

tPXIZ

11tCLCL - 5

£ CST £ 7

PSEN High to Data Address, Port 4 CE,

Port 5 PCE Valid

tPHAV

tCHCL - 3

2tCLCL - 5

CST =0

RD Pulse Width (P3.7 or PSEN)

tRLRH

(4 x CST) tCLCL - 3

£ CST £ 7

2tCLCL - 5

CST =0

WR Pulse Width (P3.6)

tWLWH

(4 x CST)tCLCL - 3

£ CST £ 7

2tCLCL - 17

CST = 0

RD (P3.7 or PSEN) Low to Valid Data In

tRLDV

(4 x CST)tCLCL - 17

£ CST £ 7

Data Hold After

RD (P3.7 or PSEN) High

tRHDX

-2

tCLCL - 5

CST = 0

2tCLCL - 5

£ CST £ 3

Data Float After

RD (P3.7 or PSEN) High

tRHDZ

6tCLCL - 5

£ CST £ 7

2tCLCL - 3

CST = 0

3tCLCL - 3

£ CST £ 3

PSEN High to WR Low

tPHWL

11tCLCL - 3

£ CST £ 7

2tCLCL - 3

CST = 0

3tCLCL - 3

£ CST £ 3

PSEN High to (RD or PSEN) Low

tPHRL

11tCLCL - 3

£ CST £ 7

3tCLCL - 19

CST = 0

(4 x CST + 2)tCLCL- 19

£ CST £ 3

Port 7 Address to Valid Data In

tAVDV1

(4 x CST + 10)tCLCL -

£ CST £ 7

3tCLCL + tCLCH - 19

CST = 0

(4 x CST + 2)tCLCL +

tCLCH - 19

£ CST £ 3

Port 2, 4, 6 Address, Port 4 CE or Port 5

PCE to Valid Data In

tAVDV2

(4 x CST + 10)tCLCL +

tCLCH - 19

£ CST £ 7

tCLCL - 5

CST = 0

2tCLCL - 5

£ CST £ 3

Port 7 Address to (

RD or PSEN) or WR

Low

tAVWL1

10tCLCL - 5

£ CST £ 7

tCLCL + tCLCH - 5

CST = 0

2tCLCL + tCLCH - 5

£ CST £ 3

Port 2, 4, 6 Address, Port 4 CE or Port 5

PCE to (

RD or PSEN) or WR Low

tAVWL2

10tCLCL + tCLCH - 5

£ CST £ 7

Data Valid to

WR Transition

tQVWX

tCLCL - 4

CST = 0

2CLCL - 7

£ CST £ 3

Data Hold After

WR High

tWHQX

6tCLCL - 7

£ CST £ 7

tCHCL - 5

tCHCL + 13

CST = 0

tCLCL + tCHCL - 5

tCLCL + tCHCL +12

£ CST £ 3

(

RD or PSEN) or WR High to Port 4 CE

or Port 5 PCE High

tWHCEH

5tCLCL + tCHCL -5

5tCLCL + tCHCL +12

£ CST £ 7

Note 1: Specifications to -40°C are guaranteed by design and not production tested.

Note 2: All parameters apply to both commercial and industrial temperature operation unless otherwise noted.

Note 3: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL, tCLCH, tCHCL are time periods

associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.

Note 4: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE,

PSEN, RD, and WR with 100pF. The following

signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (

CE0-3, A16–A19), Port 5.4–5.7

(

PCE0-3), Port 6.0–6.5 (CE4-7, A20, A2), Port 7 (demultiplexed mode A0–A7).

Note 5: References to the XTAL or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for determing

absolute signal timing with respect to the external clock.

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