CS5126 datasheet(12/32 Pages) CIRRUS

12 / 32 page

at 30kHz and 45kHz. Meanwhile, digital filters

such as the SM5805 shown in Figure 10 will

roll-off rapidly from 22kHz to 28kHz and reject

distortion energy in the second, third, and fourth

harmonics. Clearly, oversampling results in su-

perior system-level distortion.

Still, if the CS5126’s distortion performance

with high-frequency, high-amplitude signals

must be enhanced in 2X oversampling schemes,

the TRKL or TRKR outputs can be used. Either

TRKL or TRKR will fall at the end of each con-

version cycle depending on which channel is be-

ing acquired. The AINL and TRKL connections

(or AINR and TRKR) can be used as shown in

Figure 11 to control an external low-distortion

sample/hold to create an effective dc input for

the CS5126 and remove sampling distortion.

Digital Circuit Connections

When TTL loads are utilized the potential for

crosstalk between digital and analog sections of

the system is increased. This crosstalk is due to

high digital supply and signal currents arising

from the TTL drive current required of each

digital output. Connecting CMOS logic to the

digital outputs is recommended. Suitable logic

families include 4000B, 74HC, 74AC, 74ACT,

and 74HCT.

The CS5126 has a power down mode, initiated

by bringing SLEEP low. During power down,

the A/D Converter’s calibration information is

retained. The CS5126 may be used for conver-

sion immediately after SLEEP is brought high.

AINL

TRKL

S/H

L/R

+5V

Left

Analog In

Figure 11. High-Slew Monaural Connections

Signal

Amplitude

Relative to

Full Scale

Input Frequency

0dB

-20dB

-40dB

-60dB

-80dB

-100dB

-120dB

48kHz

Sampling Rate: 96 kHz

Full Scale: 9V p-p

S/(N+D): 91.44 dB

1 kHz

(dc to 20 kHz)

S/(N+D): 95.25 dB

Figure 12. FFT Plot of CS5126 in Monaural 2X Over-

sampling Mode

+5V

AINL

L/R

AINL

L/R

DINL

IBO

IBCK

DINR

SM5805

Digital Filter

Left Channel

Analog In

Right Channel

Analog In

Anti Alias

Filter

Anti Alias

Filter

CS5126

SCLK

SDATA

HOLD

SCLK

SDATA

HOLD

CLKIN

CKIN

OBCK

WDCK

LRCK

DOL

DATA IN

f s

512 f s

256 f s

32 f s

2 f s

System

Figure 10. Example Oversampling System Diagram

CS5126

DS32F1

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