CS5126 datasheet(7/32 Pages) CIRRUS

7 / 32 page

each conversion finishes determines which chan-

nel is acquired and tracked. The L/R input must

remain valid at least until 30ns before the next

falling transition on HOLD.

As shown in the timing diagram in Figure 3, the

CS5126 uses pipelined data transmission. That

is, data from a particular conversion transmits

during the next conversion cycle. The serial

clock input, SCLK, is derived by dividing the

master clock by 16. The MSB (most-significant-

bit) will be stable on the first rising edge of

SCLK after a falling transition on HOLD. With

a serial clock of fclk/16, transmission of all 16

output bits will span an entire conversion and

acquisition cycle.

STEREO MODE PERFORMANCE

As illustrated in Figure 4, the CS5126 typically

provides 92dB S/(N+D) and 0.001% THD. Un-

like conventional successive-approximation

ADC’s, the CS5126’s signal-to-noise and dy-

namic range are not limited by differential non-

linearities (DNL) caused by calibration errors.

Rather, the dominant noise source is broadband

thermal noise which aliases into the baseband.

This white broadband noise also appears as an

idle channel noise of 1/2 LSB (rms).

VA+

VA-

VD+

VD-

AINL

AINR

VREF

AGND

REFBUF

L/R

HOLD

SCLK

CLKIN

SDATA

DGND

+5V

-5V

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

Right Ch.

Analog In

Left Ch.

Analog In

/256

clk

/16

clk

fclk

/512

clk

µF

+ 1 µF

µF

+ 1 µF

Voltage

Reference

CS5126

Ω

200

Ω

200

Ω

Anti Alias

Filter

Anti Alias

Filter

1 nF

SLEEP

1 nF

Figure 2. Stereo Mode Connection Diagram

SCLK (i)

L/R (i)

HOLD (i)

Rch Conv.

Lch Conv.

Rch Acq.

Lch Acq.

LSB

MSB

LSB

MSB

LSB

MSB

SDATA (o)

Internal

Status

Right Channel Data

Left Channel Data

Figure 3. Stereo Mode Timing

CS5126

DS32F1

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