CS4812 datasheet(7/36 Pages) CIRRUS

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CS4812

DS291PP3

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE

(TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF)

Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK.

12. CDOUT should NOT be sampled during this time period.

13. DSPCLK frequency is twice the DSP instruction rate.

14. Timing is guaranteed by characterization. Production test guarantees functionality.

Parameter

Symbol

Min

Max

Unit

SPI Slave Mode (SPI/I2C = 0, SCPM/S = 0, Note 14)

CCLK Clock Frequency

fsck

-6

MHz

CCLK Low Time

tscl

CCLK High Time

tsch

Rise Time of Both CDIN and CCLK Lines

-100

Fall Time of Both CDIN and CCLK Lines

-100

Setup Time CDIN to CCLK Rising

tcdisu

Hold Time CCLK Rising to CDIN

(Note 11)

tcdih

Time from CCLK edge to CDOUT Valid

(Note 12)

tscdov

-45

Rise Time for CDOUT

tcdor

-25

Fall Time for CDOUT

tcdof

-25

CS Falling to CCLK Rising

tcss

Time from CCLK Falling to CS Rising

tsccsh

High Time Between Active CS

tcsht

µs

Time from CCLK Rising to REQ Rising

(Note 13)

tscrh

-2*DSPCLK+10

Rise Time for REQ

trr

-100

Fall Time for REQ

trf

-100

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