ADSP-TS101S datasheet(24/48 Pages) AD

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24 / 48 page

Rev. C

Page 24 of 48

May 2009

ADSP-TS101S

Table 25. Power-Up Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

tSTART_LO

RESET Deasserted After VDD, VDD_A, VDD_IO, SCLK/LCLK, and

Static/Strap Pins Are Stable and Within Specification

2ms

tPULSE1_HI

RESET Deasserted for First Pulse

50  tSCLK

100  tSCLK

tPULSE2_LO

RESET Asserted for Second Pulse

100  tSCLK

tTRST_PWR

TRST Asserted During Power-Up Reset

2  tSCLK

1 Applies after VDD, VDD_A, VDD_IO, and SCLK/LCLK and static/strap pins are stable and within specification, and before RESET is deasserted.

Figure 14. Power-Up Reset Timing

Table 26. Normal Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

tRST_IN

RESET Asserted

100  tSCLK

tSTRAP

RESET Deasserted After Strap Pins Stable

Figure 15. Normal Reset (Hot Reset) Timing

RESET

TRST

tTRST_PW R

tSTART_LO

VDD, VDD_A, VDD_IO,

SCL K/LCLK,

STAT IC/STR AP

PINS

tPULSE1_HI

tPULSE2_LO

RESET

STRAP PINS

tRST_IN

tSTRAP

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