ADSP-TS101S datasheet(2/48 Pages) AD

2 / 48 page

Rev. C

Page 2 of 48

May 2009

ADSP-TS101S

TABLE OF CONTENTS

Features ................................................................. 1

Benefits ................................................................. 1

Table of Contents ..................................................... 2

Revision History ...................................................... 2

General Description ................................................. 3

Dual Compute Blocks ............................................ 4

Data Alignment Buffer (DAB) .................................. 4

Dual Integer ALUs (IALUs) .................................... 4

Program Sequencer ............................................... 5

On-Chip SRAM Memory ........................................ 5

External Port

(Off-Chip Memory/Peripherals Interface) ................ 6

DMA Controller ................................................... 7

Link Ports ........................................................... 9

Timer and General-Purpose I/O ............................... 9

Reset and Booting ................................................. 9

Low Power Operation ............................................ 9

Clock Domains .................................................... 9

Output Pin Drive Strength Control ......................... 10

Power Supplies ................................................... 10

Filtering Reference Voltage and Clocks .................... 10

Development Tools ............................................. 10

Designing an Emulator-Compatible

DSP Board (Target) .......................................... 11

Additional Information ........................................ 11

Pin Function Descriptions ........................................ 12

Pin States at Reset ................................................ 12

Pin Definitions ................................................... 12

Strap Pin Function Descriptions ................................ 19

Specifications ........................................................ 20

Operating Conditions ........................................... 20

Electrical Characteristics ....................................... 20

Absolute Maximum Ratings ................................... 21

ESD Caution ...................................................... 21

Package Information ............................................ 21

Timing Specifications ........................................... 21

Output Drive Currents ......................................... 32

Test Conditions .................................................. 34

Environmental Conditions .................................... 36

PBGA Pin Configurations ........................................ 37

Outline Dimensions ................................................ 43

Surface-Mount Design ............................................. 44

Ordering Guide ..................................................... 45

REVISION HISTORY

5/09—Rev. B to Rev. C

Added parameter value (IDD_A max) in

Operating Conditions ............................................. 20

Updated footnotes in 484-Ball PBGA (B-484) ............... 43

Updated footnotes in 625-Ball PBGA (B-625) ............... 44

Added surface-mount design info

in Surface-Mount Design ......................................... 44

Updated models in Ordering Guide ............................ 45

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