AFE032 datasheet(46/77 Pages) TI1

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AFE032

SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

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Table 22. REG_VREF/ZEROX Register (Address = 08h)

Zero-cross1

Zero-cross2

Zero-cross3

PA_NRF

TX_RX_NRF

DAC_NRF

Reserved

detect enable

enable

R/W

LEGEND: R/W = read and write; R = read-only.

Bit 7

Zero-cross1 detect enable

This bit enables and disables the zero-crossing 1 detector.

0 = Disabled (default)

1 = Enabled

Bit 6

Zero-cross2 detect enable

This bit enables and disables the zero-crossing 2 detector.

0 = Disabled (default)

1 = Enabled

Bit 5

Zero-cross3 detect enable

This bit enables and disables the zero-crossing 3 detector.

0 = Disabled (default)

1 = Enabled

Bit 4

PA_NRF enable

This bit enables and disables the PA noise-reducing filter (NRF) and internal reference bias generator. For normal

operation, this bit is enabled. This bit is disabled during operational conditions requiring maximum power savings.

The device cannot transmit when this bit is disabled.

0 = Disabled (default)

1 = Enabled

Bit 3

TX_RX_NRF enable

This bit enables and disables the Tx and Rx NRF and internal reference bias generator. For normal operation, this

bit is enabled. This bit is disabled during operational conditions requiring maximum power savings. The device

cannot transmit or receive when this bit is disabled.

0 = Disabled (default)

1 = Enabled

Bit 2

DAC_NRF enable

This bit enables and disables the DAC NRF and internal reference bias generator. For normal operation, this bit is

enabled. This bit is disabled during operational conditions requiring maximum power savings. The device cannot

transmit when this bit is disabled.

0 = Disabled (default)

1 = Enabled

Bits[1:0]

Reserved

These bits are reserved.

Default = 0

Table 23. RESERVED Register (Address = 09h)

Reserved

LEGEND: R = read-only.

This register is reserved. Default = 18h

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