TS68C429AMFBSLASHC datasheet(30/43 Pages) ATMEL

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TS68C429A

2120A–HIREL–08/02

Figure 27. Self-test Register

The self-test register can be split in three parts:

bit 0: Used to enable receiver wrong parity detection. This bit has been imple-

mented to guarantee compatibility with previous designs:

0: Receiver wrong parity detection disable,

1: Receiver wrong parity detection enable.

Self-test command:

bit 5: Receiver test clock mode:

0: If CLK-SYS is less or equal to 10 MHz,

1: If CLK-SYS is higher than 10 MHz.

bit 6: Start transmitter self-test if a 0 to 1 transition is programmed (before a new

self-test, the user must reprogram this bit to 0).

bit 7: Start receiver Label Control Matrix self-test if a 0 to 1 transition is programmed

(before a new self-test, the user must reprogram this bit to 0).

Self-test result:

bit 8: 0: Transmitter 1 self-test is running,

1: End of Transmitter 1 self-test.

bit 9: 0: Transmitter 2 self-test is running,

1: End of Transmitter 2 self-test.

bit 10: 0: Transmitter 3 self-test is running,

1: End of Transmitter 3 self-test.

bit 11: Result of Transmitter 1 self-test:

0: (if bit 8 is set to 1) self-test pass,

1: Self-test fail.

bit 12: Request of Transmitter 2 self-test:

0: (if bit 9 is set to 1) self-test pass,

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