TS68C429AMFBSLASHC datasheet(2/43 Pages) ATMEL

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TS68C429A

2120A–HIREL–08/02

Hardware Overview

The TS68C429A is a high performance ARINC 429 controller designed to interface pri-

mary to the Atmel TS68K family microprocessor in a straight forward fashion (see

“Application Notes” on page 33). It can be connected to any TS68K processor family

with an asynchronous bus with some additional logic in some cases.

As shown in Figure 1, the TS68C429A is divided into five main blocks, the microproces-

sor interface unit (MIU), the logical control unit (LCU), the interrupt control unit (ICU), the

receiver channel unit (RCU) and the transmitter channel unit (TCU).

•

The MIU handles the interface protocol of the host processor. Through this unit, the

host sees the TS68C429A as a set of registers.

•

The LCU controls the internal data flow and initializes the TS68C429A.

•

The ICU manages one interrupt line for the RCU and one for the TCU. Each of

these two parts has a daisy chain capability. All channels have a dedicated vectored

interrupt answer. Receiver channels priority is programmable.

•

The RCU is composed of 8 ARINC receiver channels made of:

–

a serial to parallel converter to translate the two serial signals (the “1” and “0”

in RZ code) into two 16-bit words,

–

a memory to store the valid labels,

–

a control logic to check the validity of the received message,

–

a buffer to keep the last valid received message.

•

The TCU is composed of three ARINC transmitter channels made of:

–

a parallel to serial converter to translate the messages into two serial signals

(the “1” and “0” in RZ code),

–

a FIFO memory to store eight 32-bit ARINC messages,

–

a control logic to synchronize the message transmitter (parity, gap, speed,

etc.).

•

Test facility: Rx inputs can be internally connected to TX3 output.

•

Self-test facility: The receiver control label matrix and transmitter FIFO can be

tested. This self-test can be used to verify the integrity of the TS68C429A

memories.

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