Modes of Operation

The AT88SC101/102 has four operation modes selected by PGM, RST, CLK, and by the internal counter:

Inputs

Micro Instructions

PGM

RST

CLK

Definitions

RESET

X

0

The address counter is reset to 0 and the first bit of the

memory is available on I/O after the falling edge of RST

and CLK hit 0. Note: The INC instruction is disabled

when RST is high (Figure 1). Address counter is reset

on the falling edge of RESET.

INC

(INC/READ)

00

The address counter is incremented and the first bit is

available on I/O after the falling edge of the clock (unless

reading is forbidden) (Figure 2). Address increments on

falling edge of CLK. Data is released after the falling

edge of CLK.

CMP

(INC/CMP)

00

Comparison of the bit presented to the card to the

internal bit of the memory (for secret codes only). The

bit should stay stable on I/O during the time CLK is

low. The address counter is incremented on the falling

edge of the CLK (Figure 3).

WRITE

VERIFY

1

0

0

0

I/O must be positioned on 0 for programming or on 1

for erasure before the rising edge of CLK which must

stay on 1 for at least 5ms. The bit addressed (which

will be written) is available on I/O after the falling edge

of the CLK (Figure 4).

Notes:1.Output is disabled (Hi state) on addresses where read is disabled.

3.The 2 instructions CMP and UP are coded (0,0) on CLK and PGM. The circuit will distinguish between the 2 instructions

by testing the internal address counter (CMP can only be done with the addresses corresponding to the security code

or erase key).

4.The internal address counter counts up to 1519 for 101and 1567 for 102. An additional INC sets the counter to 0.

AT88SC101/102

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