Memory Access to AT88SC101 and AT88SC102

The access to the memory is controlled by the state of the internal fuses and by the voltage supply applied on the FUS pad:

FUS Pad

Voltage

State of the FUSES

FUSE 1FUSE 2

Access Conditions See:

0V

Either

Either

Table 2

5V

Blown

Not Blown

Table 1

5V

Blown

Blown

Table 2

Table 1.

AT88SC101/102 Access Conditions During Personalization (FUSE 2 Not Blown)

Zones

S

C

1

P

R

1

R

D

2

P

R

2

R

D

E

Z

1

E

Z

2

E

C

READ

WRITE 1

(Erase)

WRITE 0

(PROG)

Compare

FZ

XXXXXXX

X

YES

NO

NO

NO

IZ

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

YES

YES

NO

YES

NO

YES

NO

NO

SC

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NO

YES

NO

YES

NO

YES

YES

NO

SCAC

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

YES

YES

NO

YES

YES

YES

NO

NO

CPZ

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

YES

YES

NO

YES

NO

YES

NO

NO

AZ1

0

0

1

X

X

X

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NO

YES

YES

NO

NO

YES

NO

NO

YES

NO

NO

NO

EZ1

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NO

YES

NO

YES

NO

YES

NO

NO

AZ2

0

0

1

X

X

X

X

X

X

X

X

X

0

1

X

X

X

X

X

X

X

X

X

X

NO

YES

YES

NO

NO

YES

NO

NO

YES

NO

NO

NO

EZ2

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NO

YES

NO

YES

NO

YES

NO

NO

EC

0

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

YES

YES

NO

YES

YES

YES

NO

NO

MTZ

XXXXXXX

X

YES

YES

YES

NO

Notes:

SC:SC = 1 after validation of security code

1PR:1st bit of AZ1 (Bit 176)

1RD:2nd bit of AZ1(Bit 177)

2PR:1st bit of AZ2 (Bit 736) - AT88SC102 only

2RD:

2nd bit of AZ2 (Bit 737) - AT88SC102 only

EZ1:

EZ1 = 1 after a valid presentation of erase key 1

EZ2:

EZ2 = 1 after a valid presentation of erase key 2

EC:

EC = 1 when the counter is not empty.

AT88SC101/102

3