AS3517 datasheet(84/94 Pages) AMSCO

84 / 94 page

AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

Table 87 Second Interrupt Register

Name

Base

Default

IRQ_ENRD_1

2-wire serial

00h

Second Interrupt Register

Offset: 24h

Please be aware that writing to this register will enable/disable the corresponding

interrupts, while with reading you get the actual interrupt status and will clear the

settings. This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

SD_TIME

R/W

Control bit which sets the emergency shut-down time from

5.4sec to 10.9sec. The shut-down of AS3517 is invoked by a

high signal at the PWRUP input pin.

0: 5.4sec

1: 10.9sec

n/a

Enables interrupt which is invoked whenever a high signal at

the PWRUP input pin occurs

0: disable

1: enable

PWRUP_IRQ

This bit is set whenever a high level of min. BVDD/3 at the

PWRUP input pin occurs (PWRUP pin is commonly connected

to the power-up button)

Enables interrupt which is invoked whenever a wake-up from

RTC wake-up counter occurs

0: disable

1: enable

WAKEUP_IRQ

This bit is set when a wake-up has been invoked by the RTC

wake-up counter.

Enables interrupt which is invoked by reaching a voltage

threshold at MIC2 input (voice activation)

0: disable

1: enable

VOXM2_IRQ

This bit is set when a voltage threshold of 5mVRMS (unfiltered)

at MIC2 has been reached (voice activation)

Enables interrupt which is invoked by reaching a voltage

threshold at MIC1 input (voice activation)

0: disable

1: enable

VOXM1_IRQ

This bit is set when a voltage threshold of 5mVRMS (unfiltered)

at MIC1 has been reached (voice activation)

CVDD3_EN_SD

Invokes shut-down of AFE when a –10% under-voltage spike at

CVDD2 occurs

0: disable

1: enable

CVDD3_UNDER

This bit is set when a –5% under-voltage at CVDD1 occurs

CVDD3_EN_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

CVDD2

0: disable

1: enable

CVDD3_OVER

This bit is set when a +8% over-voltage at CVDD1 occurs

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