www.austriamicrosystems.com/AS1121

Revision 1.01

16 - 21

AS1121

Datasheet - Detailed Descr i pti on

Greyscale PWM Operation

The falling edge of the OEN signal initiates a greyscale PWM cycle. The first GSCLK pulse after the falling edge of OEN increments the grey-

scale counter by one and switches on any OUTn whose greyscale value does not equal zero. Each subsequent rising edge of GSCLK incre-

ments the greyscale counter by one.

The AS1121 compares the greyscale value of each OUTn channel with the greyscale counter value. All OUTn whose greyscale values equal the

counter values are switched off. A OEN = 1 signal after 4096 GSCLK pulses resets the greyscale counter to zero and completes a greyscale

PWM cycle (see Figure 24).

Figure 24. Greyscale PWM Cycle Timing Diagram

Output Delay

To minimize the ripple on the inrush current, the outputs are delayed and are not switching at the same time. The 16 channels of the AS1121 are

combined in groups of 4. The channels within the groups OUT0:OUT3, OUT4:OUT7, OUT8:OUT11, OUT12:OUT15 are switching at the same

20).

factory set and can be changed on request. For further information and requests, please contact us mailto:sales@austriamicrosystems.com.

Greyscale PWM

Cycle n

Greyscale

PWM

Cycle n+1

1

23

4096

OEN

GSCLK

OUT0:OUT3

Current

XERR

OUT4:OUT7

Current

OUT8:OUT11

Current

OUT12:OUT15

Current

all LED’s OFF

all LED’s ON