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AS1121

Datasheet - Detailed Descr i pti on

Setting Greyscale Brightness

The brightness of each channel output can be adjusted using a 12 bits-per-channel PWM control scheme which results in 4096 brightness steps,

from 0% to 100% brightness. The brightness level for each output is calculated as:

Where:

GSn is the programmed greyscale value for OUTn (GSn = 0 to 4095);

n = 0 to 15 greyscale data for all outputs.

The device powers up with the following default seetings: GS = 4095 and DC = 63.

The input shift register shifts greyscale data into the greyscale register for all channels simultaneously. The complete greyscale data format con-

sists of 16 x 12 bit words, which forms a 192-bit wide data packet (see Figure 21).

Note:

The data packet must be clocked in with the MSB first.

Figure 21. Greyscale Data Packet Format

When pin MODE is tied to GND, the AS1121 enters greyscale data input mode. The device switches the input shift register to 192-bit width. After

all data is clocked in, the rising edge of the LD signal latches the data into the greyscale register (see Figure 22).

All greyscale data in the input shift register is replaced with status information data (SID) after latching into the greyscale register.

Figure 22. Greyscale Data Input Timing Diagram

%Brightness =

GSn

4095

(EQ 4)

x 100

GS15.11

MSB

191

GS0.0

GS0.11

GS1.0

GS14.11

GS15.0

LSB

GS OUT0

GS OUT14:GS OUT1

...

...

...

GS OUT15

180

179

12

11

0

DCn-1

MSB

DCn-1

MSB-1

x

x

SIDn

MSB

SIDn

MSB-1

SIDn

MSB-2

SIDn

LSB

GSn

LSB

GSn

MSB

DCn-1

LSB

GSn+1

MSB

GSn+1

LSB

MODE

LD

SDI

CLK

SDO

1st Greyscale Mode

Data Input Cycle After Dot Correction Input

Following Greyscale Mode

Data Input Cycle

Dot Correction Mode

Data Input Cycle

96

1

192

1

192

x

SIDn

MSB