MSC1202Y2RHHT datasheet(54/92 Pages) TI1

54 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

www.ti.com

I2C Control (I2CCON)

Reset Value

SFR 9Ah

SBIT3

SBIT2

SBIT1

SBIT0

STOP

START

DCS

CNTSEL

00h

SBIT3−0

Serial Bit Count. Number of bits transferred (read-only).

bits 7−4

SBIT3:0

COUNT

0x00

0x01

0x03

0x02

0x06

0x07

0x05

0x04

0x0C

STOP

Stop-Bit Status.

bit 3

0: No stop

1: Stop condition received and I2C (bit 3, SFR A7h) set (cleared on write to I2CDATA)

START

Start-Bit Status.

bit 2

0: No stop

1: Start or repeated start condition received and I2C (bit 3, SFR A7h) set (cleared on write to I2CDATA)

DCS

Disable Serial Clock Stretch.

bit 1

0: Enable SCL stretch (cleared by firmware or START condition)

1: Disable SCL stretch

CNTSEL

Counter Select.

bit 0

0: Counter IRQ set for bit counter = 8 (default)

1: Counter IRQ set for bit counter = 1

SPI Data (SPIDATA) / I2C Data (I2CDATA)

Reset Value

SFR 9Bh

00h

SPIDATA

SPI Data. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are

bits 7−0

separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the

transmit interrupt.

I2CDATA

I2C Data. Data for I2C is read from or written to this location. The I2C transmit and receive buffers are

bits 7−0

separate registers, but both are addressed at this location.

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