STM32F107RB datasheet(63/103 Pages) STMICROELECTRONICS

63 / 103 page

STM32F105xx, STM32F107xx

Electrical characteristics

Doc ID 15274 Rev 6

63/104

5.3.16

Communications interfaces

2C interface characteristics

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage

conditions summarized in Table 9.

The STM32F105xx and STM32F107xx I

2C interface meets the requirements of the

standard I

2C communication protocol with the following restrictions: the I/O pins SDA and

SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and VDD is disabled, but is still present.

The I

2C characteristics are described in Table 41. Refer also to Section 5.3.12: I/O current

injection characteristics for more details on the input/output alternate function characteristics

(SDA and SCL).

Table 41.

I2C characteristics

Symbol

Parameter

Standard mode I2C(1)

Guaranteed by design, not tested in production.

Fast mode I2C(1)(2)

fPCLK1 must be at least 2 MHz to achieve standard mode I

2C frequencies. It must be at least 4 MHz to

achieve the fast mode I2C frequencies and it must be a mulitple of 10 MHz in order to reach I2C fast mode

maximum clock 400 kHz.

Unit

Min

Max

Min

Max

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

0(3)

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

period of SCL signal.

0(4)

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

900(3)

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

20 + 0.1Cb

300

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

th(STA)

Start condition hold time

4.0

0.6

µs

tsu(STA)

Repeated Start condition

setup time

4.7

0.6

tsu(STO)

Stop condition setup time

4.0

0.6

μs

tw(STO:STA)

Stop to Start condition time

(bus free)

4.7

1.3

μs

Capacitive load for each bus

line

400

STM32F107RB bảng dữ liệu(PDF) 63 Page - STMicroelectronics

STM32F107RB bảng dữ liệu(HTML) 63 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL