PM6652 datasheet(31/53 Pages) STMICROELECTRONICS

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PM6652

Device description

Doc ID 16867 Rev 5

31/53

high efficiency at light load.

Figure 8 and Figure 11 show the inductor current waveform

when the DPRSLPVR pin is asserted high or low.

When the DPRSLPVR control pin is still asserted high and the VDAC ramp-up transition is

requested, the render suspend fast exit is performed, by increasing the VDAC output with a

minimum voltage slew-rate of 10 mV//µs (

Figure 26).

If the DPRSLPVR signal is de-asserted before any VIDs change, the VDAC ramp-up

transition is performed with a minimum voltage slew-rate of 5 mV/µs (render suspend slow

exit).

In CPU IMVP6.5 and VR11 mode the minimum voltage slew-rate is fixed, as reported in

Table 8, and the DPRSLPVR control signal, when asserted high, directly activates the

pulse-skipping algorithm for higher light load efficiency.

8.7

Current sensing

As reported in

Equation 9 the voltage sensed between the CSNS and VOUT pins must be

proportional to the output current. Two main techniques can be used: the precision RSNS

resistor and the inductor's DCR current sensing (

Figure 29 and Figure 30). The first method

is more precise and more expensive, since a dedicated precision component must be

selected; on the other hand, the inductor's current sensing technique is cheaper but it's

based on the parasitic inductor resistance whose accuracy is hardly lower than 10%. An RS-

CS filter matched with the inductor's time constant is also required. If the inductor's DCR

value is greater than the required droop an additional RB resistor is necessary. In this case,

the sensed current as suggested by

Equation 9 becomes:

Equation 9

Figure 29.

Precision resistor current sensing

Figure 30.

Inductor's DCR current sensing

DCR

LOAD

DCR

OUT

SNS

⋅

−

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