PM6652 datasheet(29/53 Pages) STMICROELECTRONICS

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PM6652

Device description

Doc ID 16867 Rev 5

29/53

8.3

Pulse-skip working mode

The PM6652 can obtain very high efficiency at light load if the low-side MOSFET is turned

off when the inductor current becomes equal to zero. This feature is performed by the zero-

crossing comparator (see the internal block diagram,

Figure 24). In CPU and VR11 mode

this feature is activated by asserting the DPRSLPVR pin. In GFX render mode the

DPRSLPVR assertion implies also that the VDAC minimum slew-rate is 10 mV/µs, for

increasing the programmed output voltage, as required by IMPV6.5 specifications for render

suspend fast exit mode (refer to

Section 8.6: Voltage dynamic (VID) transitions for details).

8.4

Differential remote sensing

The PM6652 performs a differential remote sensing, between the VSNS and GSNS pins.

The error between the sensed output voltage and the programmed one (VSNS - VDAC) and

between the remote ground and local one (GSNS - GND) are the other two inputs of the

integrator, as shown in

Figure 25. The differential remote sense must be directly connected

to the mobile processor differential feedback pins; only two catch resistors

(100

Ω) are allowed to avoid any VR output voltage runaway, due to a lack of negative

feedback when the processor is not mounted.

8.5

Droop function

In order to reduce the output capacitance amount, the PM6652 performs a load dependent

behavior. The voltage sensed between pins CSNS and VOUT is proportional to the load

current:

Equation 6

Given the network shown in

Figure 25, the resulting regulated output voltage is:

Equation 7

From the previous equation the equivalent droop resistance performed by the switching

regulator is:

Equation 8

The sense resistor can be a dedicated precision resistor or the inductor's DCR as explained

Section 8.7: Current sensing.

LOAD

SNS

OUT

SNS

⋅

−

LOAD

SNS

DAC

GND

CORE

⋅

⎟⎟⎠

⎞

⎜⎜⎝

⎛

−

SNS

DROOP

⋅

⎟⎟⎠

⎞

⎜⎜⎝

⎛

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