AM79C971VCW datasheet(93/265 Pages) AMD

93 / 265 page

Am79C971

Figure 51.

Block Diagram Low Latency Receive Configuration

SRAM Accesses

The SRAM access during normal operations is a single

cycle address load to fill the upper bits into the ‘374 fol-

lowed by 17 subsequent accesses. This results in the

best utilization for the 4-FIFO arbiter in the Am79C971

controller. If the FIFO does not have enough data to

complete the full 18 cycles, the arbiter will switch after

all of the data has been written or read. This under uti-

lization occurs only at the end of a packet.

The most significant address byte EBUA_EBA[7:0] is

registered into the external ‘374 by asser tion of

AS_EBOE The least significant address byte is then

toggled on the EBUA_EBA[7:0] throughout the remain-

der of the read/write access. The data word is made up

of the most significant data byte EBDA[15:8], and the

least significant data byte EBD[7:0]. ERAMCS is con-

nected to the CE/CS chip select of the external SRAM.

AS_EBOE provides the output enable signal to the

SRAM during read operations. During write operations,

the AS_EBOE is driven high during the remainder of

the accesses. EBWE is toggled during SRAM writes.

See Figure 52 and Figure 53.

Figure 52.

Typical SRAM Read Operation

PCI Bus

Interface

Unit

802.3

MAC

Core

Expansion Bus Interface

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

20550D-54

AS_EBOE

EBUA_EBA[7:0]

EBCLK

EBD[15:0]

7:0

7:0 7:0 7:0 7:0 7:0 7:0

7:0

7:0 7:0 7:0

7:0 7:0

ERAMCS

EBWE

15:8

20550D-55

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