AM79C971VCW datasheet(257/265 Pages) AMD

257 / 265 page

F-5

5) When using Auto-polling (BCR32, bit11), the ASEL bit (BCR2, bit1) should be reset to one, in order for the MII

Auto-poll logic (this is not the same as the descriptor Auto-polling) to correctly detect the link status change

on the MII PHY.

6) During the assertion of RST#, the EECS output becomes tri-stated. It is possible that the EECS may float to a

logic high state during this time. In order to prevent a hazardous condition due to this inadvertent selection of

the EEPROM, connect a 10K pull-down resistor from EECS to ground.

7) It is recommended that each poll to the SPND bit be performed with a software implemented delay of approxi-

mately 2-3 ms intervals. When the SPND bit (CSR5, bit0) is set in the device, the time that it takes to enter the

suspend mode is dependant on several factors. Some of these factors are; the number of packets queued for

transmission in the internal memory, the received packets still in the internal memory, the PCI bus grant time,

and the transmit channel availability in the half-duplex mode. To minimize unnecessary PCI Bus activity and

allow access to the PCI bus, it is recommended that each poll to the SPND bit be performed with a software

implemented delay of approximately 2-3 ms intervals. Successive polling or polling implemented with a hard-

ware delay will inhibit the device from completing its RX/TX DMA, causing longer delays before the device to

enter suspend mode.

AM79C971VCW bảng dữ liệu(PDF) 257 Page - Advanced Micro Devices