AM53CF94JC datasheet(48/76 Pages) AMD

48 / 76 page

P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

1tPWL

Clock Pulse Width Low

0.4

• tCP

0.6

• tCP

2tCP

Clock period (1

÷ Clock Frequency)

Synchronization latency

54.58

• tCP

4tPWH

Clock Pulse Width High

0.4

• tCP

0.6

• tCP

1tPWL1

Clock Pulse Width Low

14.58

0.65

• tCP

2tCP

Clock period (1

÷ Clock Frequency)

100

3tL

Synchronization latency

54.58

tPWL + tCP

4tPWH1

Clock Pulse Width High

14.58

0.65

• tCP

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Clock Input

Note:

Clock Frequency Range for Fast Clk disabled.

= 10 MHz to 25 MHz for Asynchronous transmission

= 12 MHz to 25 MHz for Synchronous transmission

1For Synchronous data transmissions, the following conditions

must be true:

2tCP + tPWL

> 97.92 ns

2tCP + tPWH

> 97.92 ns

FastClk Disabled (Control Register Three (0CH) bit 3=0)

Note:

Clock Frequency Range for Fast Clk enabled.

= 20 MHz to 40 MHz for Asynchronous Transmission

= 20 MHz to 40 MHz for Synchronous Transmission

FastClk Enabled (Control Register Three (0CH) bit 3=1)

CLK

17348B-37

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