AD9517-0ABCPZ datasheet(18/80 Pages) AD

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AD9517-0

Data Sheet

Rev. E | Page 18 of 80

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9517-0

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

STATUS

CLK

VCP

REFMON

NOTES

1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE

CONNECTED TO GROUND FOR PROPER OPERATION.

REF_SEL

SYNC

CLK

OUT7 (OUT7A)

OUT5 (OUT5A)

OUT6 (OUT6A)

OUT4 (OUT4A)

OUT6 (OUT6B)

OUT7 (OUT7B)

OUT5 (OUT5B)

OUT4 (OUT4B)

Figure 6. Pin Configuration

Table 20. Pin Function Descriptions

Pin No.

Input/

Output

Pin Type

Mnemonic

Description

3.3 V CMOS

REFMON

Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,

3.3 V CMOS

Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,

Power

VCP

Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V. This pin is usually 3.3 V for

most applications; but if a 5 V external VCXO is used, this pin should be 5 V.

3.3 V CMOS

Charge Pump (Output). Connects to external loop filter.

3.3 V CMOS

STATUS

Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.

3.3 V CMOS

REF_SEL

Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ

pull-down resistor.

3.3 V CMOS

SYNC

Manual Synchronizations and Manual Holdover. This pin initiates a manual

synchronization and is also used for manual holdover. Active low. This pin has an

internal 30 kΩ pull-up resistor.

Loop filter

Loop Filter (Input). Connects to VCO control voltage node internally. This pin has

31 pF of internal capacitance to ground, which may influence the loop filter design

for large loop bandwidths.

Loop filter

BYPASS

This pin is for bypassing the LDO to ground with a capacitor.

10, 24, 25,

30, 31, 36,

37, 43, 45

Power

3.3 V Power Pins.

Differential

clock input

CLK

Along with CLK, this is the self-biased differential input for the clock distribution

section. This pin can be left floating if internal VCO is used.

Differential

clock input

CLK

Along with CLK, this is the self-biased differential input for the clock distribution

section. This pin can be left floating if internal VCO is used.

3.3 V CMOS

SCLK

Serial Control Port Data Clock Signal.

3.3 V CMOS

Serial Control Port Chip Select; Active Low.

This pin has an internal 30 kΩ pull-up resistor.

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