AD9517-0ABCPZ datasheet(13/80 Pages) AD

13 / 80 page

Data Sheet

AD9517-0

Rev. E | Page 13 of 80

DELAY BLOCK ADDITIVE TIME JITTER

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER1

Incremental additive jitter

100 MHz Output

Delay (1600 µA, 0x1C) Fine Adj. 000000b

0.54

ps rms

Delay (1600 µA, 0x1C) Fine Adj. 101111b

0.60

ps rms

Delay (800 µA, 0x1C) Fine Adj. 000000b

0.65

ps rms

Delay (800 µA, 0x1C) Fine Adj. 101111b

0.85

ps rms

Delay (800 µA, 0x4C) Fine Adj. 000000b

0.79

ps rms

Delay (800 µA, 0x4C) Fine Adj. 101111b

1.2

ps rms

Delay (400 µA, 0x4C) Fine Adj. 000000b

1.2

ps rms

Delay (400 µA, 0x4C) Fine Adj. 101111b

2.0

ps rms

Delay (200 µA, 0x1C) Fine Adj. 000000b

1.3

ps rms

Delay (200 µA, 0x1C) Fine Adj. 101111b

2.5

ps rms

Delay (200 µA, 0x4C) Fine Adj. 000000b

1.9

ps rms

Delay (200 µA, 0x4C) Fine Adj. 101111b

3.8

ps rms

This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SERIAL CONTROL PORT

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

µA

Input Logic 0 Current

110

µA

Input Capacitance

SCLK (INPUT)

SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

110

µA

Input Logic 0 Current

µA

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

1.1

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup and Hold, tS, tH

CS Minimum Pulse Width High, tPWH

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