PIC24HJ128GP310 datasheet(61/286 Pages) MICROCHIP

61 / 286 page

DS70175F-page 59

PIC24HJXXXGPX06/X08/X10

5.0

RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR: Master Clear Pin Reset

•SWR: RESET Instruction

• WDT: Watchdog Timer Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode and Uninitialized W

A simplified block diagram of the Reset module is

shown in Figure 5-1.

Any active source of Reset will make the SYSRST sig-

nal active. Many registers associated with the CPU and

peripherals are forced to a known Reset state. Most

registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 5-1). A POR will clear all bits, except for

the POR bit (RCON<0>), that are set. The user can set

or clear any bit at any time during code execution. The

RCON bits only serve as status bits. Setting a particular

Reset status bit in software does not cause a device

Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

Note:

This data sheet summarizes the features

this

group

of PIC24HJXXXGPX06/X08/X10 devices.

It is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to the

“PIC24H Family Reference Manual”.

Refer

the

Microchip

web

site

(www.microchip.com)

for

the

latest

PIC24H

Family

Reference

Manual

sections.

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

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