PIC24HJ128GP310 datasheet(25/286 Pages) MICROCHIP

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DS70175F-page 23

PIC24HJXXXGPX06/X08/X10

3.0

MEMORY ORGANIZATION

The PIC24HJXXXGPX06/X08/X10 architecture fea-

tures separate program and data memory spaces and

buses. This architecture also allows the direct access

of program memory from the data space during code

execution.

3.1

Program Address Space

The

program

address

memory

space

the

PIC24HJXXXGPX06/X08/X10 devices is 4M instructions.

The space is addressable by a 24-bit value derived from

either the 23-bit Program Counter (PC) during program

execution, or from table operation or data space remap-

ping as described in Section 3.4 “Interfacing Program

and Data Memory Spaces”.

User access to the program memory space is restricted

to the lower half of the address range (0x000000 to

0x7FFFFF). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

Memory maps for the PIC24HJXXXGPX06/X08/X10

family of devices are shown in Figure 3-1.

Note:

This data sheet summarizes the features

of this group of PIC24HJXXXGPX06/X08/

X10 devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to the “PIC24H Family Reference

Manual”. Refer to the Microchip web site

(www.microchip.com)

for

the

latest

PIC24H

Family

Reference

Manual

sections.

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