AX2000 datasheet(105/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

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Table 2-90 • Two RAM Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Mode

tWDASU

Write Data Setup vs. WCLK

1.39

1.59

1.87

tWDAHD

Write Data Hold vs. WCLK

0.00

tWADSU

Write Address Setup vs. WCLK

1.39

1.59

1.87

tWADHD

Write Address Hold vs. WCLK

0.00

tWENSU

Write Enable Setup vs. WCLK

1.39

1.59

1.87

tWENHD

Write Enable Hold vs. WCLK

0.00

tWCKH

WCLK Minimum High Pulse Width

0.75

tWCLK

WCLK Minimum Low Pulse Width

1.76

tWCKP

WCLK Minimum Period

2.51

Read Mode

tRADSU

Read Address Setup vs. RCLK

1.71

1.94

2.28

tRADHD

Read Address Hold vs. RCLK

0.00

tRENSU

Read Enable Setup vs. RCLK

1.71

1.94

2.28

tRENHD

Read Enable Hold vs. RCLK

0.00

tRCK2RD1

RCLK-To-OUT (Pipelined)

1.43

1.63

1.92

tRCK2RD2

RCLK-To-OUT (Non-Pipelined)

2.26

2.58

3.03

tRCLKH

RCLK Minimum High Pulse Width

0.73

tRCLKL

RCLK Minimum Low Pulse Width

1.89

tRCKP

RCLK Minimum Period

2.62

Note:

Timing data for these two cascaded RAM blocks uses a depth of 8,192. For all other combinations, use

Microsemi’s timing software.

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