AGLP030 datasheet(85/134 Pages) MICROSEMI

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IGLOO PLUS Low Power Flash FPGAs

Revision 16

2-71

Table 2-95 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V

Parameter

Description

Std. Units

tAS

Address setup time

1.28

tAH

Address hold time

0.25

tENS

REN, WEN setup time

1.13

tENH

REN, WEN hold time

0.13

tDS

Input data (WD) setup time

1.10

tDH

Input data (WD) hold time

0.55

tCKQ1

Clock High to new data valid on RD (output retained)

6.56

tCKQ2

Clock High to new data valid on RD (pipelined)

2.67

tC2CRWH1

Address collision clk-to-clk delay for reliable read access after write on same address –

applicable to opening edge

0.29

tC2CWRH1

Address collision clk-to-clk delay for reliable write access after read on same address –

applicable to opening edge

0.36

tRSTBQ

RESET Low to data out Low on RD (flow through)

3.21

RESET Low to data out Low on RD (pipelined)

3.21

tREMRSTB

RESET removal

0.93

tRECRSTB

RESET recovery

4.94

tMPWRSTB RESET minimum pulse width

1.18

tCYC

Clock cycle time

10.90

FMAX

Maximum frequency

MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

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