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PIC18F8722IPTSQTP bảng dữ liệu(PDF) 59 Page - Microchip Technology |
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PIC18F8722IPTSQTP bảng dữ liệu(HTML) 59 Page - Microchip Technology |
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59 / 446 page  © 2008 Microchip Technology Inc. DS39646C-page 57 PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu (3) TOSL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu (3) STKPTR 6X27 6X22 8X27 8X22 00-0 0000 uu-u uuuu uu-u uuuu(3) PCLATU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---u uuuu PCLATH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PCL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 PC + 2(2) TBLPTRU 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu TBLPTRH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TBLPTRL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TABLAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PRODH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 6X27 6X22 8X27 8X22 0000 000x 0000 000u uuuu uuuu (1) INTCON2 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 6X27 6X22 8X27 8X22 1100 0000 1100 0000 uuuu uuuu (1) INDF0 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC0 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC0 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC0 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW0 6X27 6X22 8X27 8X22 N/A N/A N/A FSR0H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu FSR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu WREG 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC1 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC1 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC1 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW1 6X27 6X22 8X27 8X22 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. |
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