TAS5731MPHPR datasheet(51/68 Pages) TI1

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TAS5731M

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SLOS838B – JULY 2013 – REVISED NOVEMBER 2013

MODULATION LIMIT REGISTER (0x10)

The modulation limit is the maximum duty cycle of the PWM output waveform.

Table 13. Modulation Limit Register (0x10)

MODULATION LIMIT

–

99.2%

–

98.4%

–

97.7% (1)

–

96.9%

–

96.1%

–

95.3%

–

94.5%

–

93.8%

–

RESERVED

(1)

Default values are in bold.

INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)

Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

Table 14. Channel Interchannel Delay Register Format

BITS DEFINITION

FUNCTION

–

Minimum absolute delay, 0 DCLK cycles

–

Maximum positive delay, 31 × 4 DCLK cycles

–

Maximum negative delay, –32 × 4 DCLK cycles

RESERVED

SUBADDRESS

Delay = (value) × 4 DCLKs

0x11

–

Default value for channel 1 (1)

0x12

–

Default value for channel 2 (1)

0x13

–

Default value for channel 1 (1)

0x14

–

Default value for channel 2 (1)

(1)

Default values are in bold.

ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.). Therefore,

appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD

mode, then update these registers before coming out of all-channel shutdown.

AD MODE

BD MODE

0x11

0x12

0x13

0x14

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