DMVA3 datasheet(2/287 Pages) TI1

2 / 287 page

DMVA3, DMVA4

SPRS872B – MAY 2013 – REVISED DECEMBER 2013

www.ti.com

270° Orientation and Mirroring

• Dual Controller Area Network (DCAN) Module

• General-Purpose Memory Controller (GPMC)

– CAN Version 2 Part A, B

– 8- or 16-Bit Multiplexed Address and Data

• Four Inter-Integrated Circuit (I2C Bus™) Ports

Bus

• Two Multichannel Audio Serial Ports (McASP)

– 512MB of Total Address Space Divided

– Six Serializer Transmit and Receive Ports

Among up to 8 Chip Selects

– Two Serializer Transmit and Receive Ports

– Glueless Interface to NOR Flash, NAND

– DIT-Capable For S/PDIF (All Ports)

Flash (BCH/Hamming Error Code Detection),

• Four Audio Tracking Logic (ATL) Modules

SRAM and Pseudo-SRAM

• One Serial ATA (SATA) 3.0 Gbps Controller

– Error Locator Module (ELM) Outside of

with Integrated PHY

GPMC to Provide up to 16-Bit or 512-Byte

– Direct Interface to 1 Hard Disk Drive

Hardware ECC for NAND

– Hardware-Assisted Native Command

– Flexible Asynchronous Protocol Control for

Queuing (NCQ) from up to 32 Entries

Interface to FPGA, CPLD, ASICs, and More

– Supports Port Multiplier and Command-

• Enhanced Direct Memory Access (EDMA)

Based Switching

Controller

• Real-Time Clock (RTC)

– Four Transfer Controllers

– One-Time or Periodic Interrupt Generation

– 64 Independent DMA Channels

• Up to 125 General-Purpose I/O (GPIO) Pins

– 8 QDMA Channels

• One Spin Lock Module with up to 128 Hardware

• Ethernet Switch with Dual 10-, 100-, or

Semaphores

1000-Mbps External Interfaces (EMAC

• One Mailbox Module with 12 Mailboxes

Software)

• On-Chip ARM ROM Bootloader (RBL)

– IEEE 802.3 Compliant (3.3-V I/O Only)

• Power, Reset, and Clock Management

– MII/RMII/GMII/RGMII Media Independent

– SmartReflex™ Technology (Level 2b)

Interfaces

– Multiple Independent Core Power Domains

– Management Data I/O (MDIO) Module

– Multiple Independent Core Voltage Domains

– Reset Isolation

– Support for Multiple Operating Points per

– IEEE 1588 Time-Stamping and Industrial

Voltage Domain

Ethernet Protocols

– Clock Enable and Disable Control for

• Dual USB 2.0 Ports with Integrated PHYs

Subsystems and Peripherals

– USB2.0 High- and Full-Speed Clients

• 32KB of Embedded Trace Buffer™ (ETB™) and

– USB2.0 High-, Full-, and Low-Speed Hosts

5-pin Trace Interface for Debug

– Supports End Points 0-15

• IEEE 1149.1 (JTAG) Compatible

• One PCI Express 2.0 Port with Integrated PHY

• 609-Pin Pb-Free BGA Package (AAR Suffix),

– Single Port with 1 Lane at 5.0 GT/s

0.8-mm Effective Pitch with Via Channel

– Configurable as Root Complex or Endpoint

Technology to Reduce PCB Cost (0.5-mm Ball

• Eight 32-Bit General-Purpose Timers

Spacing)

(Timer1–8)

• 45-nm CMOS Technology

• One System Watchdog Timer (WDT0)

• 1.8- and 3.3-V Dual Voltage Buffers for General

• Three Configurable UART/IrDA/CIR Modules

I/O

– UART0 with Modem Control Signals

– Supports up to 3.6864 Mbps

– SIR, MIR, FIR (4.0 MBAUD), and CIR

• Four Serial Peripheral Interfaces (SPIs) (up to

48 MHz)

– Each with Four Chip Selects

• Three MMC/SD/SDIO Serial Interfaces (up to

48 MHz)

– Supporting up to 1-, 4-, or 8-Bit Modes

High-Performance System-on-Chip (SoC)

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