ADSP-BF607 datasheet(91/112 Pages) AD

91 / 112 page

Rev. 0

Page 91 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

General-Purpose Port Timing

Table 57 and Figure 44 describe general-purpose 

port operations.

Timer Cycle Timing

Table 58 and Figure 45 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (fSCLK0/4) MHz. The Period Value value is the timer

period assigned in the TMx_TMRn_PER register and can range

from 2 to 232 – 1.

Table 57. General-Purpose Port Timing

VDD_EXT

1.8 V/3.3 V Nominal

Parameter

Min

Max

Unit

Timing Requirement

tWFI

General-Purpose Port Pin Input Pulse Width

2 × tSCLK0

Figure 44. General-Purpose Port Timing

GPIO INPUT

tWFI

Table 58. Timer Cycle Timing

Parameter

VDD_EXT

1.8V Nominal

VDD_EXT

3.3 V Nominal

Min

Max

Min

Max

Unit

Timing Requirements

tWL

Timer Pulse Width Input Low (Measured In

SCLK0 Cycles)

2 × tSCLK0

tWH

Timer Pulse Width Input High (Measured In

SCLK0 Cycles)

2 × tSCLK0

Switching Characteristics

tHTO

Timer Pulse Width Output (Measured In

SCLK0 Cycles)

tSCLK0 × Period

Value

tSCLK0 × Period

Value

tSCLK0 × Period

Value

tSCLK0 × Period

Value

1 The minimum pulse widths apply for TMx signals in width capture and external clock modes.

Figure 45. Timer Cycle Timing

TMR OUTPUT

TMR INPUT

tWH, tWL

tHTO

ADSP-BF607 bảng dữ liệu(PDF) 91 Page - Analog Devices

ADSP-BF607 bảng dữ liệu(HTML) 91 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL