MCZ33903CD3EKSLASHR2 datasheet(49/106 Pages) FREESCALE

49 / 106 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

33903/4/5

FUNCTIONAL DEVICE OPERATION

BEHAVIOR AT POWER UP AND POWER DOWN

DEVICE POWER UP

This section describe the device behavior during ramp up,

and ramp down of VSUP/1, and the flexibility offered mainly by

the Crank bit and the two VDD under-voltage reset thresholds.

The figures below illustrate the device behavior during

VSUP/1 ramp up. As the Crank bit is by default set to 0, VDD is

enabled when VSUP/1 is above VSUP TH 1 parameters.

Figure 28. VDD Start-up Versus VSUP/1 Tramp

DEVICE POWER DOWN

The figures below illustrate the device behavior during

VSUP/1 ramp down, based on Crank bit configuration, and

VDD under-voltage reset selection.

Crank Bit Reset (INIT Watchdog Register, Bit 0 =0)

Bit 0 = 0 is the default state for this bit.

During VSUP/1 ramp down, VDD remain ON until device

enters in Reset mode due to a VDD under-voltage condition

(VDD < 4.6 V or VDD < 3.2 V typically, threshold selected by

the SPI). When device is in Reset, if VSUP/1 is below

“VSUP_TH1”, VDD is turned OFF.

Crank Bit Set (INIT Watchdog Register, Bit 0 =1)

The bit 0 is set by SPI write. During VSUP/1 ramp down,

VDD remains ON until device detects a POR and set

BATFAIL. This occurs for a VSUP/1 approx 3.0 V.

VBAT

VSUP/1

VSUP_TH1

VSUP_NOMINAL (ex 12 V)

VDD NOMINAL (ex 5.0 V)

VDD

Gnd

VDD_START UP

VDD_OFF

90% VDD_START UP

10% VDD_START UP

VDD

VSUP/1

I_VDD

VSUP slew rate

3390X

VDD_UV TH (typically 4.65 V)

RST

1.0 ms

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