5CSEA2 datasheet(13/74 Pages) ALTERA

13 / 74 page

Chapter 1: Overview for Cyclone V Device Family

1–7

Cyclone V Family Plan

February 2012

Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

Table 1–7 lists the Cyclone V SE, SX, and ST package plan that shows the FPGA GPIO

and HPS I/O counts, the maximum number of transceivers available, and the vertical

migration capability for each device package and density.

1 To verify the pin migration compatibility, use the Pin Migration View window in the

Quartus II software Pin Planner.

f For more information about the verifying the pin migration compatibility, refer to the

“I/O Management” chapter in the Quartus II Handbook.

Table 1–7. Package Plan for Cyclone V SE, SX, and ST Devices—Preliminary (1)

Device

U484

(19 mm)

U672

(23 mm)

F896

(31 mm)

GPIO

XCVR

HPS I/O

GPIO

XCVR

HPS I/O

GPIO

XCVR

HPS I/O

5CSEA2

—

161

124

—

188

—

5CSEA4

—

161

124

—

188

—

5CSEA5

—

161

124

—

188

288

—

188

5CSEA6

—

161

124

—

188

288

—

188

5CSXC4 (2)

——

—

124

188

——

—

5CSXC5 (2)

—

124

188

288

188

5CSXC6 (2)

—

124

188

288

188

5CSTD5 (3)

—

288

188

5CSTD6 (3)

—

288

188

Notes to Table 1–7:

(1) The arrows indicate the package vertical migration capability. You can also migrate your design across device densities in the same packaging

option if the devices have the same dedicated pins, configuration pins, and power pins.

(2) The transceiver counts listed are for 3-Gbps transceivers.

(3) The transceiver counts listed are for 5-Gbps transceivers.

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