EM3027

Copyright

 2013, EM Microelectronic-Marin SA

3027-DS.doc, Version 8.0, 25-Jan-13

19

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Interrupt flags (IRQflags) are

cleared by ‘0’ writing into the appropriate bit. In case of V1F, V2F and SRF bits, it is necessary

to clear also the corresponding status bits (Status) after interrupt bit.

8.11

Self-Recovery System (SRS)

The purpose of the Self-Recovery System (SRS) is to generate an internal reset in case the on-chip state machine goes

into a deadlock. The function is based on an internal counter that is periodically reset by the control logic. If the counter is

not reset on time, this reset will take place. It is executed after two voltage monitoring periods at the latest, i.e. 2s or 32s

(ThPer bit).

A possible source of a deadlock could be disturbed electrical environment (EMC problem, disturbed power supply, etc.).

SRS sets status bit SR and resets the internal logic, except Watch, Alarm and Timer parts (i.e. time informations are not

affected). Furthermore, if the SRS interrupt is enabled (SRIntE='1'), the SRF flag is set after the internal chip reset. Note,

that SROn = '1' and SRIntE = '0' after the reset.

After the internal reset, the device starts with the power-up sequence (see paragraph 8.1).

SRS is automatically enabled after power-up (SROn bit). It can be disabled by writing '0' into the SROn bit in the Control

Page.

8.12

Register Map

The address range of the EM3027 is divided into pages. The page is addressed by the five most significant bits of the

address (bits 6

… 3). The three low significant bits of the address provide selection of registers inside the page. During

address incrementing the three low significant bits

(2 … 0) are changed. The page address part is fixed during the whole

data transmission.

8.13

Crystal Oscillator and Prescaler

The 32.768 kHz crystal oscillator and the clock divider provide the timing signals for the functional blocks. The prescaler

block is responsible for frequency division of the 32.768 kHz clock signal from the crystal oscillator. Divided frequency is

then distributed between other blocks inside the chip, including Watch, Timer and control logic.

Figure 5: Oscillator Capacitors