ISP1507CBS datasheet(45/74 Pages) NXP

45 / 74 page

ISP1507C_ISP1507D_1

Product data sheet

Rev. 01 — 28 May 2008

45 of 74

NXP Semiconductors

ISP1507C; ISP1507D

ULPI HS USB host and peripheral transceiver

10.1.3 INTF_CTRL register

The INTF_CTRL register enables alternative interfaces. All of these modes are optional

features provided for legacy link cores. Setting more than one of these ﬁelds results in

undeﬁned behavior. Table 25 provides the bit allocation of the register.

Table 24.

FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit

description

Bit

Symbol

Description

reserved

SUSPENDM

Suspend LOW: Active LOW PHY suspend.

Places the PHY into low-power mode. The PHY will power down all blocks, except the

full-speed receiver, OTG comparators and ULPI pins.

To come out of low-power mode, the link must assert STP. The PHY will automatically clear

this bit when it exits low-power mode.

0b — Low-power mode

1b — Powered (default)

RESET

Reset: Active HIGH transceiver reset.

After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not

reset the ULPI interface or the ULPI register set.

When reset is completed, the PHY will deassert DIR and automatically clear this bit, followed

by an RXCMD update to the link.

0b — Do not reset (default)

1b — Reset

The link must wait for DIR to deassert before using the ULPI bus. Does not reset the ULPI

interface or the ULPI register set.

4 to 3

OPMODE[1:0]

Operation Mode: Selects the required bit-encoding style during transmit.

00b — Normal operation (default)

01b — Non-driving

10b — Disable bit-stufﬁng and NRZI encoding

11b — Do not automatically add SYNC and EOP when transmitting; must be used only for

high-speed packets

TERMSELECT

Termination Select: Controls the internal 1.5 k

Ω full-speed pull-up resistor and 45 Ω

high-speed terminations. Control over bus resistors changes, depending on

XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in

Table 7.

1 to 0

XCVRSELECT[1:0]

Transceiver Select: Selects the required transceiver speed.

00b — Enable the high-speed transceiver

01b — Enable the full-speed transceiver

10b — Enable the low-speed transceiver

11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is

automatically preﬁxed)

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