PCA9554AD datasheet(9/35 Pages) NXP

9 / 35 page

PCA9554_9554A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 19 March 2013

9 of 35

NXP Semiconductors

PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

6.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins change state and

the pin is configured as an input. The interrupt is deactivated when the input returns to its

previous state or the Input Port register is read.

Note that changing an I/O from and output to an input may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input Port register.

6.4 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input with a weak pull-up (100 k

 typ.) to V

DD. The input voltage may be

raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the

state of the Output Port register. Care should be exercised if an external voltage is applied

to an I/O configured as an output because of the low-impedance paths that exist between

the pin and either VDD or VSS.

Remark: At power-on reset, all registers return to default values.

Fig 8.

Simplified schematic of IO0 to IO7

VDD

IO0 to IO7

output port

configuration

data from

shift register

write configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity inversion

002aac493

data from

shift register

VSS

to INT

100 k

PCA9554AD bảng dữ liệu(PDF) 9 Page - NXP Semiconductors

PCA9554AD bảng dữ liệu(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

bảng dữ liệu tải về

Link URL