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TMS320C6670AXCYP2 bảng dữ liệu(HTML) 2 Page - Texas Instruments |
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2 / 226 page  2 Release History Copyright 2012 Texas Instruments Incorporated SPRS689D—March 2012 Data Manual www.ti.com TMS320C6670 Release History For detailed revision information, see ‘‘Revision History’’ on page A-219. Revision Date Description/Comments D March 2012 Updated PASS PLL section (block diagram, PASS PLL Control Register, and initialization sequence) Updated Switch Fabric Matrix tables with bridge numbers and added Switch Fabric block diagrams Updated the JTAGID register table Restricted Output_Divide of SECCTL to max value of divide by 2 Changed TPTCn to EDMA3TCn and TPCCn to EDMA3CCn throughout the data manual Replaced all INTC with CIC and CPT with Tracer throughout the document Updated main PLL lock time Added DDR3PLL and PASS PLL Reset bits in DDR3PLLCTL1 and PASSPLLCTL1 registers Added the DDR3PLL and PASSPLL Initialization Sequence Added po_vcon_smpserr_intr SmartReflex event Corrected the SPI and DDR3/Hyperbridge Config Memory Map end address C October 2011 Added DEVSPEED Register section Removed Parameter Information section from chapter 7 as the content was not relevant Added more description to Boot Sequence section Changed all footnote references from CORECLK to SYSCLK1 Corrected the typo in the address of MACID2 Re-arranged the wording for description of SYSCLK1 Removed example from footnote Updated footnote on AIF jitter value to 4 ps RMS B August 2011 Revised the INTC1 Events Input table, description for BWADJ field, and power sequencing timing tables and diagrams Removed all mentions of HHV and the Max parameters for PHY Sync and Radio Sync Pulses Updated the GMacs and GFlops for 1.2 GHz and changed output skew time for the trace from 500 ps to 1ns Added thermal values to the thermal resistance characteristics table, and Power Supply to Peripheral I/O Mapping table Added register and field description table for DDR3PLLCTL1, PASSPLLCTL1, and SerDes status and config registers Corrected RESET electrical timing parameters Updated all PLL block Diagrams – Main PLL, DDR PLL, and PASS PLL Completed all tables in Device Operating Conditions chapter Updated/Added Master and Priv ID tables, added MasterID Settings table Added MMR space A April 2011 Updated the power-up sequencing section. RESETFULL must always de-assert after POR Updated the description of VARIANT bit field in JTAGID register Added Setup and Hold times for RP1CLK and RP1CLK signals, and BWADJ field to DDR3PLLCTL and PASSPLLCTL Corrected the size of TETBs for the 4 cores from 16k to 4k Added RSV0A and RSV0B pins to the terminal list table Revised power rail terminology and changed reference parameter in t2c description from t7 to t6 Added a note on Level Interrupts and EOI values for various modules Corrected the address range for I 2C MMRs and corrected extended temp max to 100C from 105C SPRS689 February 2011 Initial Release |
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