AD-DPGIOZ datasheet(46/61 Pages) AD

46 / 61 page

AD9961/AD9963

Data Sheet

Rev. A | Page 46 of 60

DRIVING THE CLOCK INPUT

For optimum performance, the AD9961/AD9963 clock inputs

(CLKP and CLKN) should be clocked with a low jitter, fast rise

time differential signal. This signal should be ac-coupled to the

CLKP and CLKN pins via a transformer or capacitors. The

CLKP/CLKN inputs are internally biased and require no

external bias circuitry. Figure 66 through Figure 69 show

preferred methods for clocking the AD9961/AD9963.

0Ω

0.1µF

50Ω*

CLK

*50Ω RESISTORS ARE OPTIONAL.

CLK_N

CLK_P

ADC

AD9963

LVDS DRIVER

CLK+

CLK–

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515/

AD9516/AD9518

Figure 66. Differential LVDS Sample Clock

In applications where the receive analog input signals and the

transmit analog output signals are at low frequencies, it is

acceptable to drive the sample clock inputs with a single-ended

CMOS signal. In such applications, CLKP should be driven

directly from a CMOS gate, and the CLKN pin should be bypassed

to ground with a 0.1 μF capacitor in parallel with a 39 kΩ

resistor (see Figure 67). A series termination resistor off the

clock driver output may improve the dynamic response of the

driver.

0.1µF

Ω

CLK

0.1µF

CLK_N

CLK_P

ADC

AD9963

OPTIONAL

100Ω

39kΩ

CMOS DRIVER

CLK+

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515/

AD9516/AD9518

Figure 67. Single-Ended 1.8 V CMOS Sample Clock

100

Ω

0.1µF

240

Ω

240

Ω

Ω*

CLK

*50

Ω RESISTORS ARE OPTIONAL.

CLK_N

CLK_P

ADC

AD9963

PECL DRIVER

CLK+

CLK–

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515/

AD9516/AD9518

Figure 68. Differential PECL Sample Clock

0.1µF

SCHOTTKY

DIODES:

HSM2812

CLK+

50Ω

CLK_N

CLK_P

Mini-Circuits®

ADT1-1WT, 1:1Z

XFMR

ADC

AD9963

Figure 69. Transformer Coupled Clock

Note that the 39 kΩ resistor shown in the CMOS clock driver

example shifts the CLK_N input to about 0.9 V. This is optimal

when the CMOS driver is supplied from a 1.8 V supply.

A 2.5 V CMOS driver may also be used. In this case, the

minimum CLK33V supply voltage should be 2.5 V. The 39 kΩ

resistor should be removed in this case. Connecting CLKN to

ground with just a 0.1 µF capacitor results in the CLKN voltage

being biased to about 1.2 V.

Clock Duty Cycle Considerations

The duty cycle of the input clock should be maintained between

45% and 55%. Duty cycles outside of this range affects the

dynamic performance of the ADC. This is especially true at

sample rates greater than 75 MHz. It is recommended that the

duty cycle stabilizer (DCS) be used at clock rates above 75 MHz

to ensure the sampling clock maintains the proper duty cycle

inside the device. Below 75 MHz, the DCS should be bypassed.

The DCS is bypassed by setting Register 0x66, Bit 2 high.

DLL Duty Cycle Caution

Stability of the DLL output requires the main clock input to

have a duty cycle of 50% or less. In systems where the duty cycle

is greater than 50%, care should be taken to swap the CLKP and

CLKN pins to reverse this effect.

CLOCK MULTIPLICATION USING THE DLL

The AD9961/AD9963 contain a recirculating DLL, as shown in

Figure 70. This circuit allows the incoming CLK signal

(REFCLK) to be multiplied by a programmable M/N factor.

This provides a means of generating a wide range of DLL output

clock (DLLCLK) frequencies. The DLLCLK signal can be used

for either the receive ADC sampling clock, the transmit DAC

sampling clock, or both. The EXTDLLCLK signal can be

programmed to appear on the TXCLK pin or TRXCLK if

desired.

AD-DPGIOZ bảng dữ liệu(PDF) 46 Page - Analog Devices

AD-DPGIOZ bảng dữ liệu(HTML) 46 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

bảng dữ liệu tải về

Link URL