AD-DPGIOZ datasheet(39/61 Pages) AD

39 / 61 page

Data Sheet

AD9961/AD9963

Rev. A | Page 39 of 60

Interpolation Filter Coefficients

The interpolation filters, INT0 and INT1, are half-band filters

implemented with a symmetric set of coefficients. Every other

coefficient (even coefficients) except the center coefficient is

zero. The coefficient values for the three interpolation filters are

listed in Table 17 to Table 19.

Table 17. Coefficient Values for INT0

Lower Coefficient

Upper Coefficient

Value

H(1)

H(43)

H(3)

H(41)

−32

H(5)

H(39)

H(7)

H(37)

−140

H(9)

H(35)

252

H(11)

H(33)

−422

H(13)

H(31)

682

H(15)

H(29)

−1086

H(17)

H(27)

1778

H(19)

H(25)

−3284

H(21)

H(23)

10364

H(22)

16384

Table 18. Coefficient Values for INT1

Lower Coefficient

Upper Coefficient

Value

H(1)

H(19)

H(3)

H(17)

−138

H(5)

H(15)

466

H(7)

H(13)

−1314

H(9)

H(11)

5058

H(10)

8191

Table 19. Coefficient Values for SRRC Filter

Lower Coefficient

Upper Coefficient

Value

H(1)

H(53)

−2

H(2)

H(52)

−2

H(3)

H(51)

H(4)

H(50)

−4

H(5)

H(49)

−21

H(6)

H(48)

H(7)

H(47)

H(8)

H(46)

−29

H(9)

H(45)

−79

H(10)

H(44)

H(11)

H(43)

123

H(12)

H(42)

−127

H(13)

H(41)

−183

H(14)

H(40)

232

H(15)

H(39)

251

H(16)

H(38)

−394

H(17)

H(37)

−326

H(18)

H(36)

642

H(19)

H(35)

401

H(20)

H(34)

−1034

H(21)

H(33)

−469

H(22)

H(32)

1704

H(23)

H(31)

523

H(24)

H(30)

−3160

H(25)

H(29)

−560

H(26)

H(28)

9996

H(27)

16383

Data Flow and Clock Generation

The transmit port TXD[11:0] and TXIQ signals are captured

from by the device with an input latch. The data is then

formatted and buffered in an 8-word deep FIFO. The data exits

the FIFO and is processed by whichever interpolation filters are

enabled. The data is then sampled by the transmit DACs.

The FIFO absorbs any phase drift between the two clock

domains that drive the transmit data. The data is read from the

FIFO by the RDCLK signal. The RDCLK signal is always the

DACCLK divided by the interpolation ratio, I. Data is written to

the FIFO by the WRCLK signal at the quadrature data input

rate, fDATA. fDATA is equal to one-half the bus speed because the I

and Q samples are interleaved.

Figure 52 shows the block diagram of the transmit path data

flow in full-duplex mode. Also shown in the diagram are the

input data clocking options and the clock doubler selections.

AD-DPGIOZ bảng dữ liệu(PDF) 39 Page - Analog Devices

AD-DPGIOZ bảng dữ liệu(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

bảng dữ liệu tải về

Link URL