AD9142BCPZ datasheet(6/65 Pages) AD

6 / 65 page

AD9142

Data Sheet

Rev. 0 | Page 6 of 64

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CMOS INPUT LOGIC LEVEL

Input

Logic High

DVDD18 = 1.8 V

1.2

Logic Low

DVDD18 = 1.8 V

0.6

CMOS OUTPUT LOGIC LEVEL

Output

Logic High

DVDD18 = 1.8 V

1.4

Logic Low

DVDD18 = 1.8 V

0.4

LVDS RECEIVER INPUTS

Input Voltage Range

VIA or VIB

825

1675

Input Differential Threshold

VIDTH

Data and FRAME inputs

−100

+100

DCI input

−225

+225

Input Differential Hysteresis

VIDTHH to VIDTHL

Receiver Differential Input Impedance

RIN

120

DAC UPDATE RATE

1600

MSPS

DAC Adjusted Update Rate

2× interpolation

250

MSPS

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage

Self biased input, ac-coupled

1.25

REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage

1.25

Input Clock Frequency

1 GHz ≤ fVCO ≤ 2.1 GHz

450

MHz

SERIAL PORT INTERFACE

Maximum Clock Rate

SCLK

MHz

Minimum Pulse Width

High

tPWH

12.5

Low

tPWL

12.5

Setup Time

tDS

SDIO to SCLK

1.5

Hold Time

tDH

SDIO to SCLK

0.68

Setup Time

tDCSB

CS to SCLK

2.38

1.4

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