TMS320DM6467CCUTAV datasheet(37/355 Pages) TI1

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TMS320DM6467

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SPRS403H – DECEMBER 2007 – REVISED JUNE 2012

Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

PCI_AD25/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD9/

I/O/Z

For EMIFA, this pin is address bit 9 output EM_A[9] (O/Z).

DVDD33

HD25/EM_A[9]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD24/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD8/

I/O/Z

For EMIFA, this pin is address bit 8 output EM_A[8] (O/Z).

DVDD33

HD24/EM_A[8]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD23/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD7/

I/O/Z

For EMIFA, this pin is address bit 7 output EM_A[7] (O/Z).

DVDD33

HD23/EM_A[7]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD22/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD6/

I/O/Z

For EMIFA, this pin is address bit 6 output EM_A[6] (O/Z).

DVDD33

HD22/EM_A[6]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD21/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD5/

I/O/Z

For EMIFA, this pin is address bit 5 output EM_A[5] (O/Z).

DVDD33

HD21/EM_A[5]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD20/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD4/

I/O/Z

For EMIFA, this pin is address bit 4 output EM_A[4] (O/Z).

DVDD33

HD20/EM_A[4]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD19/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD3/

I/O/Z

For EMIFA, this pin is address bit 3 output EM_A[3] (O/Z).

DVDD33

HD19/EM_A[3]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD18/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD2/

I/O/Z

For EMIFA, this pin is address bit 2 output EM_A[2] (O/Z).

DVDD33

HD18/EM_A[2]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

PCI_AD17/

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

IPD

DD1/

I/O/Z

For EMIFA, this pin is address bit 1 output EM_A[1] (O/Z).

DVDD33

HD17/EM_A[1]

This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).

This pin is multiplexed between PCI, ATA, HPI, and EMIFA.

For EMIFA, this pin is address bit 0 output EM_A[0] (O/Z), which is the least

PCI_AD16/

IPD

significant bit on a 32-bit word address.

DD0/

I/O/Z

DVDD33

When connected to a 16-bit asynchronous memory, this pin is the second bit of

HD16/EM_A[0]

the address.

For an 8-bit asynchronous memory, this pin is the third bit of the address.

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