DS32EL0421, DS32ELX0421

SNLS282F – MAY 2008 – REVISED APRIL 2013

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LVDS Timing Specifications (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

TxCLKIN Transition Time

See Figure 2

0.5

1.0

3.0

ns

TxIN Transition Time

0.15

3

ns

TxCLKIN High Time

See Figure 3

0.7T

T

1.3T

ns

TxCLKIN Low Time

0.7T

T

1.3T

ns

TxIN Setup to TxCLKIN

-550

ps

TxIN Hold to TxCLKIN

900

ps

LVDS Input Clock Delay Step Size

Programmable through the SMBus,

100

ps

register 30'h

Default setting = 011'b [7:5]

(3)

Parameter is ensured by characterization and is not tested at production.

CML Electrical Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Output Terminations

On chip termination from TxOUT0/1 +

40

50

60

Ω

50

Ω mode

75

Ω mode

60

75

90

Ω

Mismatch in Output Termination Resistors

5

%

Output Differential Voltage Swing

Based on VOD_CTRL = 9.1 k

Ω

1175

1350

1450

(1)

The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2)

Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

(3)

at the time of product characterization and are not ensured.

CML Timing Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LR

Line Rate

Tested with alternating 1-0 pattern.

1.25

3.125

Gbps

Output Overshoot

10

%

Differential Low to High Transition Time

60

90

ps

Differential High to Low Transition Time

60

90

ps

Mismatch in Rise/Fall Time

15

ps

De-emphasis width

Measured from zero-crossing at rising

1

UI

edge to 80% of VOD from zero-

crossing at falling edge. TDE is

measured at the High setting during

test.

Serializer Bit Width

0.2 x

ns

Serializer Propagation Delay – Latency

Depends on mode — see Table 3

(10 –

ns

14) T+

5.5

(1)

The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2)

at the time of product characterization and are not ensured.

(3)

Parameter is ensured by characterization and is not tested at production.

8

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