MCP4441 datasheet(15/100 Pages) MICROCHIP

15 / 100 page

DS22265A-page 15

MCP444X/446X

102A (5)

TRSCL

SCL rise time

100 kHz mode

—

1000

Cb is specified to be from

10 to 400 pF (100 pF maxi-

mum for 3.4 MHz mode)

400 kHz mode

20 + 0.1Cb

300

1.7 MHz mode

160

After a Repeated Start con-

dition or an Acknowledge

bit

3.4 MHz mode

After a Repeated Start

condition or an Acknowl-

edge bit

102B (5)

TRSDA

SDA rise time

100 kHz mode

—

1000

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode

20 + 0.1Cb

300

1.7 MHz mode

160

3.4 MHz mode

103A (5)

TFSCL

SCL fall time

100 kHz mode

—

300

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode

20 + 0.1Cb

300

1.7 MHz mode

3.4 MHz mode

103B (5)

TFSDA

SDA fall time

100 kHz mode

—

300

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode

20 + 0.1Cb (4)

300

1.7 MHz mode

160

3.4 MHz mode

106

THD:DAT Data input hold

time

100 kHz mode

—

1.8V-5.5V, Note 6

400 kHz mode

—

2.7V-5.5V, Note 6

1.7 MHz mode

—

4.5V-5.5V, Note 6

3.4 MHz mode

—

4.5V-5.5V, Note 6

TABLE 1-3:

I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I2C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40

°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max

Units

Conditions

Note 1:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the

requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before

the SCL line is released.

The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH

and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

Use Cb in pF for the calculations.

Not Tested.

A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

Ensured by the TAA 3.4 MHz specification test.

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