0 dB

-180°

-360°

LOAD ZERO

LOAD POLE

ERROR AMP

ω

LG

*

=

1 + j

(j )

ω

1 + j

(ESR x C

ω

1 + j

((ESR + R

ω

LOOP

GAIN

+

-

LP3982

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SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013

Figure 18. Simplified Model of Regulator Loop Gain Components

Figure 18 shows a basic model for the linear regulator that helps describe what happens to the output signal as it

is processed through its feedback loop; that is, describe its loop gain (LG). The LG includes two main transfer

functions: the error amplifier and the load. The error amplifier provides voltage gain and a dominant pole, while

the load provides a zero and a pole. The LG of the model in Figure 18 is described by the following equation:

(3)

The first term of the above equation expresses the voltage gain (numerator) and a single pole role-off

(denominator) of the error amplifier. The second term expresses the zero (numerator) and pole (denominator) of

Figure 19 shows a Bode plot that represents a case where the zero contributed by the load is too high to cancel

illustrates the corresponding phase shift. Notice that the phase shift at unity gain is a total 360° -the criteria for

oscillation.

Figure 19. Loop Gain Bode Plot Illustrating Inadequately High Zero for Stability Compensation

The LP3982 generates an internal zero that makes up for the inadequately high zero of the low ESR ceramic

output capacitor. This internally generated zero is strategically placed to provide positive phase shift near unity

gain, thus providing a stable phase margin.

No-Load Stability

The LP3982 remains stable during no-load conditions, a necessary feature for CMOS RAM keep-alive

applications.

Copyright © 2002–2013, Texas Instruments Incorporated

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