TMS320DM6467CCUTAV datasheet(97/355 Pages) TI

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TMS320DM6467

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SPRS403H – DECEMBER 2007 – REVISED JUNE 2012

4.4.2.2

BOOTSTAT Register

The Boot Status (BOOTSTAT) register indicates the status of the device boot process (e.g., boot error,

boot complete, or watchdog timer reset).

WDRST

RESERVED

BOOTERR

R/W-0

R-000 0000 0000

R-0000

RESERVED

R-0000 0000 0000 000

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 4-7. BOOTSTAT Register

Table 4-9. BOOTSTAT Register Bit Descriptions

BIT

NAME

DESCRIPTION

Watchdog Timer Reset.

0 = Device reset was not a result of a watchdog timer timeout.

1 = Device reset was a result of a watchdog timer timeout.

WDRST

This is a "sticky" bit that can be used to debug WD timeout conditions. The bit is set when a WD

timeout occurs (TOUT2). This bit is reset (to "0") by a POR reset only; otherwise it retains its value.

It is not cleared by a Warm Reset or Soft Reset.

The bit may be cleared by writing a "1".

30:20

RESERVED

Reserved. Read returns "0".

Boot Error.

0000 = No boot error [default].

19:16

BOOTERR

Others = Bootloader detected boot error.

The exact meaning of the various error codes will be determined by the bootloader software.

15:1

RESERVED

Reserved. Read returns "0".

Boot Complete.

0 = Host has not completed the boot sequence [default].

1 = Host has completed the boot sequence.

This bit may be optionally set by a host boot device (such as PCI or HPI) to indicate that it has

finished loading code. The ARM926 can poll this bit to determine whether to continue the boot

process.

Device Configurations

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