DOC7707 datasheet(174/307 Pages) ETC1

174 / 307 page

174

7707F–AVR–11/10

AT90USB82/162

control logic is disabled. The USART RX and TX control logic is replaced by a common SPI

transfer control logic. However, the pin control logic and interrupt generation logic is identical in

both modes of operation.

The I/O register locations are the same in both modes. However, some of the functionality of the

control registers changes when using MSPIM.

18.2

Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. For

USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-

ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one

(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should

be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).

The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-

ter mode. The baud rate or UBRRn setting can therefore be calculated using the same

equations, see Table 18-1:

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

Baud rate (in bits per second, bps)

OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRnH and UBRRnL Registers, (0-4095)

Table 18-1.

Equations for Calculating Baud Rate Register Setting

Operating Mode

Equation for Calculating Baud Rate(1)

Equation for Calculating UBRRn Value

Synchronous Master mode

BAUD

OSC

2 UBRRn

()

---------------------------------------

UBRRn

OSC

2BAUD

--------------------

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