AM1705DPTP3 datasheet(7/164 Pages) TI1

7 / 164 page

AM1705

www.ti.com

SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013

Revision History (continued)

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 5.5.1, Power-On Reset (POR):

Section 5.5

•

Updated/Changed "RTCK is maintained active through a POR." to "RTCK/GP7[14] is maintained active

Reset

through a POR."

Section 5.5.2, Warm Reset:

•

Updated/Changed “A warm reset provides …” paragraph

•

Updated/Changed "RTCK is maintained active through a warm reset." to "RTCK/GP7[14] is maintained

active through a warm reset."

Table 5-7, AINTC System Interrupt Assignments:

Section 5.8.1.4

AINTC System

•

Updated/Changed SYSTEM INTERRUPT 27 INTERRUPT NAME from “PROTERR” to

Interrupt

“MPU_BOOTCFG_ERR”

Assignments on the

•

Updated/Changed SYSTEM INTERRUPT 27 SOURCE from “SYSCFG Protection Shared Interrupt” to

device

“Shared MPU and SYSCFG Address/Protection Error Interrupt"

Table 5-8, AINTC Memory Map:

Section 5.8.1.5

AINTC Memory Map •

Deleted "[0]" to 0xFFFE F500 "HIER" REGISTER NAME

Section 5.11

Section 5.11.2, EMIFA Connection Examples:

External Memory

•

Added new Subsection

Interface A (EMIFA)

Section 5.12

Figure 5-17, EMIFB Functional Block Diagram:

External Memory

•

Added MPU2 block to figure

Interface B (EMIFB)

Section 5.12.1, EMIFB SDRAM Loading Limitations:

•

Moved subsection from Interfacing to SDRAM section to under Section 5.12.1, External Memory

Interface B (EMIFB)

•

Updated/Changed “EMIFB supports SDRAM up to 133 MHz …” to “EMIFB supports SDRAM up to 152

MHz …”

Section 5.12.2, EMIFB Supported SDRAM Configurations:

Section 5.12.2

Interfacing to

•

Updated/Changed the table to include 8-bit SDRAM Memory Data Bus Width entries

SDRAM

•

Updated/Changed "Number of Memories" column from "2" to "1" for the 16-Bit data bus width

Table 5-25, EMIFB SDRAM Interface Switching Characteristics:

Section 5.12.4

•

Updated/Changed PARAMETER No. 1, tc(CLK) Cycle time, EMIF clock EMB_CLK MIN value from “7.5”

EMIFB Electrical

to “6.579” ns

Data/Timing

•

Updated/Changed PARAMETER No. 2, tw(CLK) Pulse width, EMIF clock EMB_CLK high or low MIN

value from “3” to “2.63” ns

Section 5.26.1

Section 5.26.1.1, Power Domain States:

Power Domain and

•

Added new subsection

Module Topology

Section 5.29.1, JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0):

Section 5.29

IEEE 1149.1 JTAG

•

Added Silicon Revisions "3.0" and "2.1" to the "0x9B7D F02F for silicon revision 2.0" bullet

Section 6.1.2

Device and

Updated/Changed subsection title from “Device Nomenclature” to “Device and Development-Support Tool

Development-

Nomenclature"

Support Tool

Nomenclature

Figure 6-1, Device Nomenclature:

•

Updated/Changed Silicon Revision to include Revision 3.0

Section 7

•

Deleted “Mechanical Drawings” section

Mechanical

•

Deleted Packaging Materials Information subsection (was Section 7.1 in the previous revision), duplicate

Packaging and

information

Orderable

•

Added Section 7.3, Packaging Information

Information

Contents

Submit Documentation Feedback

Product Folder Links: AM1705

AM1705DPTP3 bảng dữ liệu(PDF) 7 Page - Texas Instruments

AM1705DPTP3 bảng dữ liệu(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL