AM1705DPTP3 datasheet(39/164 Pages) TI1

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AM1705

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SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013

5.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

5.3

Power Supplies

5.3.1

Power-on Sequence

The device should be powered-on in the following order:

1. Core logic supplies:

(a) CVDD core logic supply

(b) Other 1.2V logic supplies (PLL0_VDDA). Groups 1a) and 1b) may be powered up together or 1a)

first followed by 1b).

2. All 1.8V IO supplies (USB0_VDDA18).

3. All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33 ).

Group 2) and group 3) may be powered on in either order [2 then 3, or 3 then 2] but group 3) must be

powered-on after the core logic supplies.

There is no specific required voltage ramp rate for any of the supplies.

RESET must be maintained active until all power supplies have reached their nominal values.

5.3.2

Power-off Sequence

The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered

with the other supplies unpowered.

5.4

Unused USB0 (USB2.0) Pin Configurations

Table 5-1. Unused USB0 Pin Configurations

SIGNAL NAME

Configuration

(When USB0 is not used)

USB0_DM

No connect

USB0_DP

No connect

USB0_VDDA33

No connect

USB0_VDDA18

No connect

USB0_VDDA12

No connect

AHCLKX0/USB_REFCLKIN/

No connect or use as alternate function

GP2[11]

Peripheral Information and Electrical Specifications

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