AD9523-1SLASHPCBZ datasheet(9/60 Pages) AD

9 / 60 page

AD9523-1

Rev. B | Page 9 of 60

JITTER AND NOISE CHARACTERISTICS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT ABSOLUTE RMS TIME JITTER

Application example based on a typical setup (see Table 3);

f = 122.88 MHz

LVPECL Mode, HSTL Mode, LVDS Mode

109

Integrated BW = 200 kHz to 5 MHz

115

Integrated BW = 200 kHz to 10 MHz

150

Integrated BW = 12 kHz to 20 MHz

177

Integrated BW = 10 kHz to 61 MHz

187

Integrated BW = 1 kHz to 61 MHz

124

Integrated BW = 1 MHz to 61 MHz

PLL2 CHARACTERISTICS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO (ON CHIP)

Frequency Range

2940

3100

MHz

Gain

MHz/V

PLL2 FIGURE OF MERIT (FOM)

−226

dBc/Hz

MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

Minimum and Low

250

MHz

Maximum and High

125

MHz

LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE

Input High

2.0

Input Low

0.8

INPUT LOW CURRENT

±80

±250

μA

The minus sign indicates that, due to the internal pull-up

resistor, current is flowing out of the AD9523-1

CAPACITANCE

RESET TIMING

Pulse Width Low

Inactive to Start of Register

Programming

100

SYNC TIMING

Pulse Width Low

1.5

High speed clock is the CLK input signal

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