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EPC2TC32 bảng dữ liệu(PDF) 18 Page - Altera Corporation

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Giải thích chi tiết về linh kiện  Configuration Devices for SRAM-Based
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EPC2TC32 bảng dữ liệu(HTML) 18 Page - Altera Corporation

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Page 18
Timing Information
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
Table 11 lists the timing parameters when using EPC1, EPC1064, EPC1064V, EPC1213,
and EPC1441 devices when configuring the FLEX 8000 device.
tOEW
OE
low pulse width (reset) to guarantee counter reset
100
—
—
ns
tOEC
OE
low (reset) to DCLK disable delay
—
—
20
ns
tNRCAS
OE
low (reset) to nCASC delay
—
—
25
ns
Note to Table 10:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Table 11. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441
Devices
Symbol
Parameter
EPC1064V
EPC1064 and
EPC1213
EPC1 and
EPC1441
Unit
Min
Max
Min
Max
Min
Max
tOEZX
OE
high to DATA output enabled
—
75
—
50
—
50
ns
tCSZX
nCS
low to DATA output enabled
—
75
—
50
—
50
ns
tCSXZ
nCS
high to DATA output disabled
—
75
—
50
—
50
ns
tCSS
nCS
low setup time to first DCLK rising edge
150
—
100
—
50
—
ns
tCSH
nCS
low hold time after DCLK rising edge
0—
0—
0—
ns
tDSU
Data
setup time before rising edge on DCLK
75
—
50
—
50
—
ns
tDH
Data
hold time after rising edge on DCLK
0—
0—
0—
ns
tCO
DCLK
to DATA out delay
—
100
—
75
—
75
ns
tCK
Clock period
240
—
160
—
100
—
ns
fCK
Clock frequency
—
4
—
6
—
8
MHz
tCL
DCLK
low time
120
—
80
—
50
—
ns
tCH
DCLK
high time
120
—
80
—
50
—
ns
tXZ
OE
low or nCS high to DATA output disabled
—
75
—
50
—
50
ns
tOEW
OE
pulse width to guarantee counter reset
150
—
100
—
100
—
ns
tCASC
Last DCLK + 1 to nCASC low delay
—
90
—
60
—
50
ns
tCKXZ
Last DCLK + 1 to DATA tri-state delay
—
75
—
50
—
50
ns
tCEOUT
nCS
high to nCASC high delay
—
150
—
100
—
100
ns



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